返回信息流在上一期热点文献推荐中,我们为您推荐了AI在气候领域的最新发展前沿,包括Google GraphCast基于机器学习精准预测未来10天全球天气情况、华为盘古气象利用3D神经网络进行精确的中期全球天气预报、NowcastNet对极端降水的临近预报、通过深度学习揭示全球变暖对日降水量的影响。
本期我们为您选取了4篇文献,介绍半导体与集成电路的最新应用,包括清华大学发表的首颗基于忆阻器的片上学习存算一体芯片“面向边缘学习的全集成忆阻器存算一体芯片”、用于高速视觉任务的全模拟光电芯片、可编程梯度掺杂用于可重构碲化钼器件、北京邮电大学屈贺如歌老师与复旦大学合作发表的“层状铁电半导体中的极化-电导耦合机制”。
文献一 面向边缘学习的全集成忆阻器存算一体芯片
Edge learning using a fully integrated neuro-inspired memristor chip
Zhang, Wenbin, etc.
SCIENCE, 2023, 381(6663): 1205–1211
Learning is highly important for edge intelligence devices to adapt to different application scenes and owners. Current technologies for training neural networks require moving massive amounts of data between computing and memory units, which hinders the implementation of learning on edge devices. We developed a fully integrated memristor chip with the improvement learning ability and low energy cost. The schemes in the STELLAR architecture, including its learning algorithm, hardware realization, and parallel conductance tuning scheme, are general approaches that facilitate on-chip learning by using a memristor crossbar array, regardless of the type of memristor device. Tasks executed in this study included motion control, image classification, and speech recognition.
阅读原文:https://www.science.org/doi/10.1126/science.ade3483
文献二 用于高速视觉任务的全模拟光电芯片
All-analog photoelectronic chip for high-speed vision tasks
Chen, Yitong, etc.
NATURE, 2023, 623: 48–57
Photonic computing enables faster and more energy-efficient processing of vision data. However, experimental superiority of deployable systems remains a challenge because of complicated optical nonlinearities, considerable power consumption of analog-to-digital converters (ADCs) for downstream digital processing and vulnerability to noises and system errors. Here we propose an all-analog chip combining electronic and light computing (ACCEL). It has a systemic energy efficiency of 74.8 peta-operations per second per watt and a computing speed of 4.6 peta-operations per second (more than 99% implemented by optics), corresponding to more than three and one order of magnitude higher than state-of-the-art computing processors, respectively. After applying diffractive optical computing as an optical encoder for feature extraction, the light-induced photocurrents are directly used for further calculation in an integrated analog computing chip without the requirement of analog-to-digital converters, leading to a low computing latency of 72 ns for each frame. With joint optimizations of optoelectronic computing and adaptive training, ACCEL achieves competitive classification accuracies of 85.5%, 82.0% and 92.6%, respectively, for Fashion-MNIST, 3-class ImageNet classification and time-lapse video recognition task experimentally, while showing superior system robustness in low-light conditions (0.14 fJ μm-2 each frame). ACCEL can be used across a broad range of applications such as wearable devices, autonomous driving and industrial inspections.
阅读原文:https://www.nature.com/articles/s41586-023-06558-8
文献三 可编程梯度掺杂用于可重构碲化钼器件
Programmable graded doping for reconfigurable molybdenum ditelluride devices
Peng, Ruixuan, etc.
NATURE ELECTRONICS, 2023, 6: 852–861
Non-volatile reconfigurable devices have the potential to improve integration levels and lower power consumption in next-generation electronics. Two-dimensional semiconductors are promising materials for making non-volatile reconfigurable devices due to their atomic thinness and strong gate control, but it is challenging to create varied reconfigurable functions with a simple device configuration. Here we show that an effective-gate-voltage-programmed graded-doping strategy can be used to create a single-gate two-dimensional molybdenum ditelluride device with multiple reconfigurable functions. The device can be programmed to function as a polarity-switchable diode, memory, in-memory Boolean logic gates and artificial synapses with homosynaptic plasticity and heterosynaptic plasticity. As a diode, the device exhibits a rectification ratio of up to 104; as an artificial heterosynapse, it shows heterosynaptic metaplasticity with a modulatory power consumption that can be reduced to 7.3 fW.
阅读原文:https://www.nature.com/articles/s41928-023-01056-1
文献四 层状铁电半导体中的极化-电导耦合机制
Asymmetric conducting route and potential redistribution determine the polarization-dependent conductivity in layered ferroelectrics
Quhe, Ruge, etc.
NATURE NANOTECHNOLOGY, 2023
Precise control of the conductivity of layered ferroelectric semiconductors is required to make these materials suitable for advanced transistor, memory and logic circuits. Although proof-of-principle devices based on layered ferroelectrics have been demonstrated, it remains unclear how the polarization inversion induces conductivity changes. Therefore, function design and performance optimization remain cumbersome. Here we combine ab initio calculations with transport experiments to unveil the mechanism underlying the polarization-dependent conductivity in ferroelectric channel field-effect transistors. We find that the built-in electric field gives rise to an asymmetric conducting route formed by the hidden Stark effect and competes with the potential redistribution caused by the external field of the gate. Furthermore, leveraging our mechanistic findings, we control the conductivity threshold in α-In2Se3 ferroelectric channel field-effect transistors. We demonstrate logic-in-memory functionality through the implementation of electrically self-switchable primary (AND, OR) and composite (XOR, NOR, NAND) logic gates. Our work provides mechanistic insights into conductivity modulation in a broad class of layered ferroelectrics, providing foundations for their application in logic and memory electronics.
阅读原文:https://www.nature.com/articles/s41565-023-01539-4
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