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在上一期热点文献推荐中，我们为您推荐了电子皮肤的最新发展前沿，包括利用纤维Bragg光栅和深层神经网络的大面积触觉敏感皮肤，可用于无线健康监测设备的基于表面声波传感器的无芯片无线电子皮肤，基于印刷突触晶体管的可感受“疼痛”的电子皮肤，一种由水凝胶和硅胶弹性体组成的具有触觉感应能力的仿生弹性机器人皮肤。本期我们为您选取了4篇文献，介绍存算一体技术的最新发展前沿，包括三星电子发表的全球首个基于MRAM交叉阵列的存内计算研究，基于阻变存储器RRAM的存算一体芯片，基于三维阻变存储器的存内计算宏芯片，基于集成铁电突触阵列的CMOS兼容存内计算加速器，推送给相关领域的科研人员。文献一用于图像分类和人脸检测的基于MRAM交叉阵列的存内计算 A crossbar array of magnetoresistive memory devices for in-memory computing Jung, Seungchul, etc. NATURE, 2022, 601(7892): 211–216 Implementations of artificial neural networks that borrow analogue techniques could potentially offer low-power alternatives to fully digital approaches(1-3). One notable example is in-memory computing based on crossbar arrays of non-volatile memories(4-7) that execute, in an analogue manner, multiply-accumulate operations prevalent in artificial neural networks. Various non-volatile memories-including resistive memory(8-13), phase-change memory(14,15) and flash memory(16-19)-have been used for such approaches. However, it remains challenging to develop a crossbar array of spin-transfer-torque magnetoresistive random-access memory (MRAM)(20-22), despite the technology's practical advantages such as endurance and large-scale commercialization(5). The difficulty stems from the low resistance of MRAM, which would result in large power consumption in a conventional crossbar array that uses current summation for analogue multiply-accumulate operations. Here we report a 64 x 64 crossbar array based on MRAM cells that overcomes the low-resistance issue with an architecture that uses resistance summation for analogue multiply-accumulate operations. The array is integrated with readout electronics in 28-nanometre complementary metal-oxide-semiconductor technology. Using this array, a two-layer perceptron is implemented to classify 10,000 Modified National Institute of Standards and Technology digits with an accuracy of 93.23 per cent (software baseline: 95.24 per cent). In an emulation of a deeper, eight-layer Visual Geometry Group-8 neural network with measured errors, the classification accuracy improves to 98.86 per cent (software baseline: 99.28 per cent). We also use the array to implement a single layer in a ten-layer neural network to realize face detection with an accuracy of 93.4 per cent. 阅读原文：https://www.nature.com/articles/s41586-021-04196-6 MRAM crossbar array 文献二基于RRAM的存内计算芯片 A compute-in-memory chip based on resistive random-access memory Wan, Weier, etc. NATURE, 2022,608(7923): 504-512 Realizing increasingly complex artificial intelligence (AI) functionalities directly on edge devices calls for unprecedented energy efficiency of edge hardware. Compute-in-memory (CIM) based on resistive random-access memory (RRAM)(1) promises to meet such demand by storing AI model weights in dense, analogue and non-volatile RRAM devices, and by performing AI computation directly within RRAM, thus eliminating power-hungry data movement between separate compute and memory(2-5). Although recent studies have demonstrated in-memory matrix-vector multiplication on fully integrated RRAM-CIM hardware(6-17), it remains a goal for a RRAM-CIM chip to simultaneously deliver high energy efficiency, versatility to support diverse models and software-comparable accuracy. Although efficiency, versatility and accuracy are all indispensable for broad adoption of the technology, the inter-related trade-offs among them cannot be addressed by isolated improvements on any single abstraction level of the design. Here, by co-optimizing across all hierarchies of the design from algorithms and architecture to circuits and devices, we present NeuRRAM-a RRAM-based CIM chip that simultaneously delivers versatility in reconfiguring CIM cores for diverse model architectures, energy efficiency that is two-times better than previous state-of-the-art RRAM-CIM chips across various computational bit-precisions, and inference accuracy comparable to software models quantized to four-bit weights across various AI tasks, including accuracy of 99.0 percent on MNIST18 and 85.7 percent on CIFAR-10(19) image classification, 84.7-percent accuracy on Google speech command recognition(20), and a 70-percent reduction in image-reconstruction error on a Bayesian image-recovery task. 阅读原文：https://www.nature.com/articles/s41586-022-04992-8 Design methodology and main contributions of the NeuRRAM chip 文献三基于三维阻变存储器的存内计算宏芯片 A computing-in-memory macro based on three-dimensional resistive random-access memory Huo, Qiang, etc. NATURE ELECTRONICS, 2022, 5(7): 469-477 Non-volatile computing-in-memory macros that are based on two-dimensional arrays of memristors are of use in the development of artificial intelligence edge devices. Scaling such systems to three-dimensional arrays could provide higher parallelism, capacity and density for the necessary vector-matrix multiplication operations. However, scaling to three dimensions is challenging due to manufacturing and device variability issues. Here we report a two-kilobit non-volatile computing-in-memory macro that is based on a three-dimensional vertical resistive random-access memory fabricated using a 55 nm complementary metal-oxide-semiconductor process. Our macro can perform 3D vector-matrix multiplication operations with an energy efficiency of 8.32 tera-operations per second per watt when the input, weight and output data are 8, 9 and 22 bits, respectively, and the bit density is 58.2 bit mu m(-2). We show that the macro offers more accurate brain MRI edge detection and improved inference accuracy on the CIFAR-10 dataset than conventional methods. 阅读原文：https://www.nature.com/articles/s41928-022-00795-x Challenges of applying 2D RRAM to large 3D CNNs and proposed 3D nvCIM scheme 文献四基于集成铁电突触阵列的CMOS兼容存内计算加速器 CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks Kim, Min-Kyu, etc. SCIENCE ADVANCES, 2022, 8(14) Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been developed, but unwanted leakage current paths and the high-power consumption remain as the challenges. Here, we demonstrate integrated ferroelectric thin-film transistor (FeTFT) synaptic arrays that can provide efficient parallel programming and data processing for CNNs by the selective and accurate control of polarization in the ferroelectric layer. In addition, three-terminal FeTFTs can act as both nonvolatile memory and access device, which tackle issues from two-terminal devices. An integrated FeTFT synaptic array with parallel programming capabilities can perform convolution operations to extract image features with a high-recognition accuracy. 阅读原文：https://www.science.org/doi/10.1126/sciadv.abm8537 Ferroelectric synaptic transistor array and parallel programming operation

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