返回信息流【求助】vhdl代码纠错
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT(CLK,CLEAR,STOP,CHOICE:IN STD_LOGIC;
WARN:OUT STD_LOGIC;
HIGH,LOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT;
ARCHITECTURE THREE OF COUNT IS
SIGNAL HS:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL LS:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,CHOICE)
BEGIN
IF clear='1' THEN
IF CHOICE='0' THEN
HS<="0011";LS<="0000";WARN<='0';
ELSE HS<="0110";LS<="0000";WARN<='0';
END IF;
ELSIF CLK'EVENT AND CLK='1' THEN
IF ((STOP='1') AND ( NOT (HS="0000" AND LS="0000"))) THEN
LS<=LS-1;
IF STOP='1' AND LS="0000" AND HS/="0000" THEN
LS<="1001";HS<=HS-1;
IF STOP='1' AND HS="0001" AND LS="0000" THEN
WARN<='1';
IF STOP='1' AND HS="0000" AND LS="0000" THEN
HS<="0000";LS<="0000";
END IF;
END IF;
END IF;
END IF;
END IF;
HIGH<=HS;LOW<=LS;
END PROCESS;
END ARCHITECTURE THREE;
下面是通过编译的一雄代码：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT IS
PORT(CLK,CLEAR,STOP:IN STD_LOGIC;
WARN:OUT STD_LOGIC;
HIGH,LOW:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COUNT;
ARCHITECTURE THREE OF COUNT IS
SIGNAL HS:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL LS:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
IF clear='1' THEN
HS<="0011";LS<="0000";WARN<='0';
ELSIF CLK'EVENT AND CLK='1' THEN
IF ((STOP='1') AND ( NOT (HS="0000" AND LS="0000"))) THEN
LS<=LS-1;
IF STOP='1' AND LS="0000" AND HS/="0000" THEN
LS<="1001";HS<=HS-1;
IF STOP='1' AND HS="0001" AND LS="0000" THEN
WARN<='1';
IF STOP='1' AND HS="0000" AND LS="0000" THEN
HS<="0000";LS<="0000";
END IF;
END IF;
END IF;
END IF;
END IF;
HIGH<=HS;LOW<=LS;
END PROCESS;
END ARCHITECTURE THREE;
设计抢答器的计时模块，本来已经通过编译了，老师说要增加一个答题计时30秒或60秒的选项，改了半天都没发现到底是哪个地方错了，后面想一下，我是用c语言的思想去编的，可能是if出错了，求大牛帮忙纠正，感激不尽......
这是一条镜像帖。来源：北邮人论坛 / circuit / #19266同步于 2011/12/9
该镜像源已超过 30 天没有更新，可能在源站已被删除。
Circuit机器人发帖
【求助】vhdl代码纠错
ghoo
2011/12/9镜像同步6 回复
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6 条回复
unsuppore error:conditional statement in this region for signal not supported
网上什么也搜不到。。。要一楼能帮我解决这问题，大颗粒感谢......
其实就一特别简单的东西，在clear='1'的基础下判断choice=1或0两种情况，然后分别给hs,ls赋值，现在已经改了整整一天......
能改出来的同学当面大颗粒感谢。。。
【 在 ghoo 的大作中提到: 】
: unsuppore error:conditional statement in this region for signal not supported
: 网上什么也搜不到。。。要一楼能帮我解决这问题，大颗粒感谢......
: --
: ...................
HIGH<=HS;LOW<=LS;
这两句话放到process外
楼主是不是这么个意思。。。
BEGIN PROCESS(CLK) BEGIN IF clear='1' THEN HS<="0011";LS<="0000";WARN<='0'; ELSIF CLK'EVENT AND CLK='1' THEN IF ((STOP='1') AND ( NOT (HS="0000" AND LS="0000"))) THEN LS<=LS-1; elsIF STOP='1' AND LS="0000" AND HS/="0000" THEN LS<="1001";HS<=HS-1; elsIF STOP='1' AND HS="0001" AND LS="0000" THEN WARN<='1'; elsIF STOP='1' AND HS="0000" AND LS="0000" THEN HS<="0000";LS<="0000"; end if； END IF; HIGH<=HS;LOW<=LS; END PROCESS; END ARCHITECTURE THREE;