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在上一期热点文献推荐中，我们为您推荐了大型语言模型在医学与生物学领域的最新发展前沿，包括由Google科研人员提出的用于评估LLM模型在临床知识方面的MultiMed QA评估基准、利用结构化和非结构化记录基于语言模型进行临床预测、大型语言模型生成跨家族可预测功能的蛋白质序列、使用大型语言模型从初级序列直接推断全原子级蛋白质结构。本期我们为您选取了4篇文献，介绍人工智能与集成电路交叉学科的最新发展前沿，包括一种用于高效语音识别与转录的模拟AI芯片，一种用于深度神经网络推理的64核混合信号存内计算芯片，提高AI边缘设备安全性的CMOS集成自旋电子nvCIM宏，用于AI边缘推理的28nm RRAM nvCIM宏。文献一一种用于高效语音识别与转录的模拟AI芯片 An analog-AI chip for energy-efficient speech recognition and transcription Ambrogio, S., etc. NATURE, 2023, 620(7975): 768–775 Models of artificial intelligence (AI) that have billions of parameters can achieve high accuracy across a range of tasks, but they exacerbate the poor energy efficiency of conventional general-purpose processors, such as graphics processing units or central processing units. Analog in-memory computing (analog-AI) can provide better energy efficiency by performing matrix-vector multiplications in parallel on 'memory tiles'. However, analog-AI has yet to demonstrate software-equivalent (SWeq) accuracy on models that require many such tiles and efficient communication of neural-network activations between the tiles. Here we present an analog-AI chip that combines 35 million phase-change memory devices across 34 tiles, massively parallel inter-tile communication and analog, low-power peripheral circuitry that can achieve up to 12.4 tera-operations per second per watt (TOPS/W) chip-sustained performance. We demonstrate fully end-to-end SWeq accuracy for a small keyword-spotting network and near-SWeq accuracy on the much larger MLPerf recurrent neural-network transducer (RNNT), with more than 45 million weights mapped onto more than 140 million phase-change memory devices across five chips. 阅读原文：https://www.nature.com/articles/s41586-023-06337-5 文献二一种用于深度神经网络推理的64核混合信号存内计算芯片 A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference Le Gallo, Manuel, etc. NATURE ELECTRONICS, 2023, 6(9): 680–693 Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal-oxide-semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix-vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively. 阅读原文：https://www.nature.com/articles/s41928-023-01010-1 文献三提高AI边缘设备安全性的CMOS集成自旋电子nvCIM宏 A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices Chiu, Yen-Cheng, etc. NATURE ELECTRONICS, 2023, 6(7): 534–543 A non-volatile compute-in-memory macro that is based on spin-transfer torque magnetic random-access memory can offer secure access control, data protection, rapid response times and high energy efficiency for dot-product edge computing. Artificial intelligence edge devices should offer high inference accuracy and rapid response times, as well as being energy efficient. Ensuring the security of these devices against malicious attacks and illegal access requires data protection mechanisms and secure access control. Here we report a spintronic non-volatile compute-in-memory macro for efficient dot-product edge computing with secure access control for activation, key and data protection against power-on and power-off probing. The approach relies on spintronic-based physically unclonable functions and two-dimensional half-complement physical encryption, as well as a snoop-proof self-decryption burst-read scheme in conjunction with a sparsity-and-rectified-linear-unit-aware early-termination compute-in-memory engine. The 6.6 megabit complementary metal-oxide-semiconductor (CMOS)-integrated macro uses 22 nm spin-transfer torque magnetic random-access memory technology. The macro achieves high randomness (inter-Hamming distance, 0.4999) and high reliability for physically unclonable functionality (intra-Hamming distance, 0), as well as a high energy efficiency for dot-product computation (between 30.1 and 68.0 tera-operations per second per watt). 阅读原文：https://www.nature.com/articles/s41928-023-00994-0 文献四用于AI边缘推理的28nm RRAM nvCIM宏 A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference Ye, Wang, etc. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2023, 58(10): 2839–2850 Non-volatile computing-in-memory (nvCIM) can potentially meet the ever-increasing demands on improving the energy efficiency (EF) for intelligent edge devices. However, it still suffers from limited input parallelism due to the parasitic effects, signal margin degradation due to device non-idealities, and large hardware cost for analog readout. In this work, we present a two-transistor-one-resistor (2T1R) resistive memory (RRAM) nvCIM macro featuring: 1) a macro structure with decoupled memory and computing data paths; 2) the weighted hybrid 2T1R (WH-2T1R) cell array; 3) the redundant sub-array mapping scheme of the most-significant-bit (RSM-MSB); and 4) reference-subtracting current sense amplifier (RS-CSA). A test-chip is silicon-verified using the 28-nm high-k/metal-gate (HKMG) logic process with foundry-developed RRAM. The test-chip performs linear analog multiply-and-accumulate (MAC) operations over 32 accumulation channels and achieves 30.34-154.04 TOPS/W with 1-bit input (IN), 3-bit weight (W), and 4-bit output (O). Evaluations with the ResNet-18 model show that the MSB-RSM scheme results in 0.96% and 2.83% improvement on CIFAR-10 and CIFAR-100 inference accuracy, respectively. 阅读原文：https://ieeexplore.ieee.org/document/10145046/ “前沿文献专题推荐服务”是图书馆情报服务部学科服务的重要内容。欢迎有相关需求的科研人员与我们联系，我们将为您提供更有针对性的定题服务。联系电话：62281933 62283502 地址：西土城校区图书馆125室沙河校区图书馆东205室联系人：杨老师闫老师邮箱：yandong80@bupt.edu.cn

热点文献带您关注AI与集成电路领域的最新进展——图书馆前沿文