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use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity ppm is
port( clk,rst,din:in std_logic;
d_en,f_en:out std_logic;
dout:out std_logic_vector(7 downto 0));
end ppm;
architecture decoder of ppm is
type state is (s0,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28);
signal clk1,clk2,b,a:std_logic;
signal count1:std_logic_vector(3 downto 0);
signal count2:std_logic_vector(1 downto 0);
signal count3:std_logic_vector(3 downto 0);
signal count4:std_logic_vector(3 downto 0);
signal out1:std_logic_vector(7 downto 0);
--signal temp:std_logic_vector(127 downto 0);
--signal temp2:std_logic_vector(7 downto 0);
signal p,s:state;
begin
process(clk,rst)
begin
if clk'event and clk='1' then
if rst='0' then
count1<="0000";
elsif count1="1111" then
count1<="0000";
else count1 <= count1+1;
end if;
end if;
end process;
process(clk,rst)
begin
if clk'event and clk='1' then
if rst='0' then
count4<="0000";
else count4<=count4+1;
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if count1<"0111" then
clk1<='0';
elsif count1="1111" then
clk1<='0';
else clk1<='1';
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='1' then
if count4="0111" then
clk2<='1';
else clk2<='0';
end if;
end if;
end process;
--process(clk)
--begin
--if clk'event and clk='1' then
--clk3<=(clk1 xor clk2);
--end if;
--end process;
process(clk1)
begin
if clk1'event and clk1='1' then
p<=s;
end if;
end process;
process(clk,rst)
begin
if rst='0' then
d_en<='0';
f_en<='0';
dout<="00000000";
elsif clk'event and clk='0' then
if clk2='1' and a='1' then
dout<=out1;
d_en<='1';
else
d_en<='0';
end if;
if clk2='1' and b='1' then
f_en<='1';
else f_en<='0';
end if;
end if;
end process;
process(rst,clk1)
begin
if rst ='0' then
s<=s0;
count2<="00";
count3<="0000";
out1<="00000000";
a<='0';
b<='0';
--d_en<='0';
--f_en<='0';
--dout<="00000000";
--temp<=x"00000000000000000000000000000000";
elsif clk1'event and clk1='0' then
case p is
when s0=>out1<=out1(6 downto 0)&din;
if out1="01111011" then
if din='1' then
s<=s9;
out1<="00000000";
end if;
else s<=s0;
end if;
when s8=>
--寮�濮嬫帴鏀舵暟鎹?
b<='0';
a<='0';
if din='1' then
s<=s9;
else s<=s0;
end if;
when s9=>if din='1' then
s<=s10;
else s<=s11;
end if;
when s10=>if din='1' then
s<=s12;
else s<=s28;
end if;
when s11=>
if din='1' then
s<=s13;
else s<=s0;
end if;
when s12=>
if din='1' then
s<=s15;
else s<=s14;
end if;
when s13=>if din='1' then
s<=s16;
else s<=s0;
end if;
when s14=>if din='1' then
s<=s17;
else s<=s0;
end if;
when s15=>if din='1' then
s<=s18;
else s<=s0;
end if;
when s16=>if din='1' then
s<=s19;
else s<=s0;
end if;
when s17=>if din='1' then
s<=s20;
else s<=s0;
end if;
when s18=>if din='0' then
s<=s21;
else s<=s22;
end if;
when s19=>if din='1' then
s<=s23;
else s<=s0;
end if;
when s20=>if din='1' then
s<=s24;
else s<=s0;
end if;
when s21=>if din='1' then
s<=s25;
else s<=s0;
end if;
when s22=>if din='1' then
s<=s26;
else s<=s0;
end if;
when s23=>if din='1' then
s<=s27;
else s<=s0;
end if;
when s24=>if din='1' then
out1<="01"&out1(7 downto 2);
if count2="11" then
count2<="00";
--dout<="01"&out1(7 downto 2);
--d_en<='1';
a<='1';
else
-- out1<="01"&out1(7 downto 2);
count2<=count2+1;
end if;
s<=s8;
else s<=s0;
end if;
when s25=>if din='1' then
out1<="10"&out1(7 downto 2);
if count2="11" then
count2<="00";
-- dout<="10"&out1(7 downto 2);
a<='1';
else
-- out1<="10"&out1(7 downto 2);
count2<=count2+1;
end if;
s<=s8;
else s<=s0;
end if;
when s26=>if din='0' then
out1<="11"&out1(7 downto 2);
if count2="11" then
count2<="00";
-- dout<="11"&out1(7 downto 2);
a<='1';
else
-- out1<="11"&out1(7 downto 2);
count2<=count2+1;
end if;
s<=s8;
else s<=s0;
end if;
when s27=>if din='1' then
out1<="00"&out1(7 downto 2);
if count2="11" then
count2<="00";
-- dout<="00"&out1(7 downto 2);
a<='1';
else
count2<=count2+1;
-- out1<="00"&out1(7 downto 2);
end if;
s<=s8;
else s<=s0;
end if;
when s28=>s<=s0;
end case;
end if;
end process;
end ;
这是一条镜像帖。来源:北邮人论坛 / circuit / #3019同步于 2007/12/25
该镜像源已超过 30 天没有更新,可能在源站已被删除。
Circuit机器人发帖
偶做的ppm解码器
fzylijun886
2007/12/25镜像同步2 回复
订阅后,新回复会通过你的通知中心匿名送达。
2 条回复
这是test-bench
Library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_unsigned.all;
entity c is
end;
architecture behav of c is
component ppm
port( clk,rst,din:in std_logic;
d_en,f_en:out std_logic;
dout:out std_logic_vector(7 downto 0));
end component;
signal clk,rst,din,d_en,f_en: std_logic;
signal dout:std_logic_vector(7 downto 0);
begin
u1: ppm port map (clk,rst,din,d_en,f_en,dout);
process
begin
clk <='0';
wait for 295 ns;
clk <='1';
wait for 295 ns;
end process;
rst <= '0','1' after 9 us;
din<='0','1' after 18.88 us,'0' after 56.64 us,'1' after 66.08 us,'0' after 113.28 us,'1' after 122.72 us,'0' after 169.92 us,'1' after 179.36 us,'0' after 283.20 us,'1' after 292.64 us,'0' after 377.6 us,'1' after 387.04 us,'0' after 405.92 us,'1' after 415.36 us,'0' after 424.80 us,'1' after 434.24 us,'0' after 472.00 us,'1' after 481.44 us,'0' after 566.40 us,'1' after 575.84 us,'0' after 641.92 us,'1' after 651.36 us,'0' after 717.44 us,'1' after 726.88 us,'0' after 792.96 us,'1' after 802.40 us,'0' after 821.28 us,'1' after 830.72 us,'0'after 840.16 us,'1' after 849.60 us,'0' after 887.36 us,'1' after 896.80 us,'0' after 944.00 us,'1' after 953.44 us,'0' after 1000.64 us,'1' after 1010.08 us,'0' after 1113.92 us,'1' after 1123.36 us,'0' after 1208.32 us,'1' after 1217.76 us,'0' after 1283.84 us,'1' after 1293.28 us,'0' after 1359.36 us,'1' after 1368.80 us,'0' after 1434.88 us,'1' after 1444.32 us,'0' after 1491.52 us,'1' after 1500.96 us,'0' after 1538.72 us,'1' after 1548.16 us;
end;
configuration cfg_tb_c of c is
for behav
end for;
end;
这是设计报告,没有转图工具就贴报告了哈
【 在 fzylijun886 的大作中提到: 】
: 这是test-bench
: Library IEEE;
: use IEEE.std_logic_1164.all;
: ...................
附件(262.5KB)