BYR Achieve · 镜像论坛

在上期的前沿文献推荐中，介绍了半导体领域的最新进展，包括：亚10纳米二维场效应晶体管：理论与实验；用于运动检测和识别的一体化二维视网膜形态的硬件设备；我们如何制作二维晶体管；用于晶圆级电子设备的对齐二维碳纳米管液晶。在本期的文献推荐中，关注点着眼于，包括：晶圆级的单层晶体管；面向未来集成电路的二维材料的晶体管；二维材料集成电路的进展情况；兼顾迁移率和稳定性的氧化物薄膜晶体管。上述文献供相关领域的科研人员参考。领域一晶圆级的单层晶体管 Monolayer transistors at wafer scales Du Xiang, etc. Nature Electronics, 2021 Monolayer transition metal dichalcogenide transistors can be fabricated on 300 mm wafers using an approach that is compatible with back-end-of-line process temperatures. https://www.nature.com/articles/s41928-021-00694-7 Fig. 2D monolayer transistors at wafer scales 领域二面向未来集成电路的二维材料的晶体管 Transistors based on two-dimensional materials for future integrated circuits Saptarshi Das, etc. Nature Electronics, 2021,4: 786–799 Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies. https://www.nature.com/articles/s41928-021-00670-1 Fig. Two-dimensional FET fabrication and characterization 领域三二维材料集成电路的进展情况 The development of integrated circuits based on two-dimensional materials Kaichen Zhu, etc Nature Electronics, 2021, 4: 775–785 Two-dimensional (2D) materials could potentially be used to develop advanced monolithic integrated circuits. However, despite impressive demonstrations of single devices and simple circuits—in some cases with performance superior to those of silicon-based circuits—reports on the fabrication of integrated circuits using 2D materials are limited and the creation of large-scale circuits remains in its infancy. Here we examine the development of integrated circuits based on 2D layered materials. We assess the most advanced circuits fabricated so far and explore the key challenges that need to be addressed to deliver highly scaled circuits. We also propose a roadmap for the future development of integrated circuits based on 2D layered materials. https://www.nature.com/articles/s41928-021-00672-z Fig. Roadmap for 2D-LM-based ICs 领域四兼顾迁移率和稳定性的氧化物薄膜晶体管 Mobility–stability trade-off in oxide thin-film transistors Yu-Shien Shiah, etc. Nature Electronics, 2021, 4: 800–807 Thin-film transistors based on amorphous oxide semiconductors could be used to create low-cost backplane technology for large flat-panel displays. However, a trade-off between mobility and stability has limited the ability of such devices to replace current polycrystalline silicon technologies. Here we show that the sensitivity of amorphous oxide semiconductors to externally introduced impurities and defects is determined by the location of the conduction-band minimum and the relevant doping ability. Using bilayer-structured thin-film transistors, we identify the exact charge-trapping position under bias stress, which shows that the Fermi-level shift in the active layer can occur via electron donation from carbon-monoxide-related impurities. This mechanism is highly dependent on the location of the conduction-band minimum and explains why carbon-monoxide-related impurities greatly affect the stability of high-mobility indium tin zinc oxide transistors but not that of low-mobility indium gallium zinc oxide transistors. Based on these insights, we develop indium tin zinc oxide transistors with mobilities of 70 cm2 (V s)–1 and low threshold voltage shifts of –0.02 V and 0.12 V under negative- and positive-bias temperature stress, respectively. https://www.nature.com/articles/s41928-021-00671-0 Fig. Universal tendency of electronic structure and electrical properties of AOSs

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