BYR Achieve · 镜像论坛

同组内推，欢迎有意向的小伙伴一起师夷长技。岗位：EDA公司Synopsys，硬件仿真器上的时钟树处理与优化。要求：有无相关工作经验均可；要求熟悉C++，有一定的英语沟通能力。有EDA、FPGA、ASIC相关背景可加分。工作地点：美国东部、美国西部、法国、上海均可。公司可协助办理工作签证（但美国L签证规定需先在国内工作一年方可申请，所以前期工作地点仍是上海）简历邮箱：synopsys211@gmail.com Synopsys Verification Group is looking for a R&D engineer (software developer) to work on the performance and clock processing aspects of its ZeBu emulation and prototyping platform. Responsibilities: - Responsible for research and development of clock processing related optimizations. Responsible for understanding performance aspects in ZeBu and identifying opportunities to improve it further. - Responsible for developing, testing, and tuning stable ASIC/FPGA algorithms targeting high quality of results (QoR) such as area, performance, congestion, compile time and power etc. - Designs, implements, tests, delivers, and maintains highly efficient algorithms and data structures. - Developing professional expertise and may apply company policies and procedures to resolve a variety of issues. - Exercises judgment to determine appropriate action. Implementations and solutions are reviewed for accuracy and overall adequacy. - Builds productive internal/external working relationships. - Contacts primarily within business unit and occasional organizational and external customer personnel on routine matters. Requirements: - PhD or master’s degree in electrical and/or Computer Engineering with with some software development experience. - Strong C++ and problem-solving skills. - Original research publications in the area of computer engineering / electronic design and verification field is a big plus. Proficiency in designing data structures, algorithms, and specs for sophisticated software products. - Basic EDA knowledge and experience in areas such logical and physical synthesis, RTL, simulation, emulation, formal verification etc. - Experience with FPGAs is a plus. - Background in netlist optimizations for area, performance, congestion, power etc. will be a plus. - Digital IC design flows (ASIC and FPGA) - Skillful in using script languages such as TCL, Python, Perl, Unix shell scripts. - Experience with developing software into a large code bases desired - Familiarity with industrial standard SW development and quality practices. Results-driven, agility, integrity and teamwork. Desire to learn and explore unfamiliar concepts, tools and techniques. - Strong communication skills, verbal and written. Ability to coordinate discussions with other R&D teams.

【内推】【校招】【社招】【海外】EDA公司Synopsys招软件工程师