返回信息流本人写了一个VHDL程序 ,要求的功能是数据进入后,可以和原来地址的数据求和后,在存如以前的地址,类似于FIFO,但仿真后,输出端,没有输出,想了半天也不明白,请那位高人指点一下. 程序如下.(还有一个数据读的功能)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ram is
generic (w:integer:=12;
k:INTEGER :=4);
port (indata:in std_logic_vector(3 downto 0);
outdata:out std_logic_vector(3 downto 0);
clk,clr,wr,rd,getin,en :in std_logic;
overram :out std_logic );
end ram;
architecture behav of ram is
type memory is array (0 to 11)of std_logic_vector(3 downto 0);
signal ran :memory;
signal rp: integer range 0 to 11:=0;
signal wp: integer range 0 to 11:=0;
signal over:std_logic;
signal data :std_logic_vector(3 downto 0);
signal odata:std_logic_vector(3 downto 0);
begin
process(indata,wr,clk)
begin
if( clk'event and clk='1')then
if (clr='1')then
clean:for wp in 0 to 11 loop
ran(wp)<=(others=>'0');
end loop clean;
else
if (en='1') then
if (wr='1' )then
data<=ran(wp);
data<=indata+data;
ran(wp)<=data;
else ran(wp)<=ran(wp);
end if ;
end if;
end if;
end if;
if(wp=11) then
wp<=0;
else
wp<=wp+1;
end if ;
end process;
process (getin,clk)
begin
if (clk'event and clk='1')then
if (getin='1' and rd='1')then
odata<=ran(rp);
end if;
end if;
if(rp=11)
then
over<='1';
else
rp<=rp+1;
over<='0';
end if;
--end if;
end process;
outdata<=odata when rd='1'
else (others=>'0');
overram<=over;
end behav;
这是一条镜像帖。来源：北邮人论坛 / communications / #2654同步于 2006/9/20
该镜像源已超过 30 天没有更新，可能在源站已被删除。
Communications机器人发帖
那位懂VHDL的大虾求助
walichun
2006/9/20镜像同步3 回复
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3 条回复
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ram is
generic (w:integer:=12;
k:INTEGER :=4);
port (indata:in std_logic_vector(3 downto 0);
outdata:out std_logic_vector(3 downto 0);
clk,clr,wr,rd,getin,en :in std_logic;
overram :out std_logic );
end ram;
architecture behav of ram is
type memory is array (0 to 11)of std_logic_vector(3 downto 0);
signal ran :memory;
signal rp: integer range 0 to 11;
signal wp: integer range 0 to 11;
signal over:std_logic;
signal data :std_logic_vector(3 downto 0);
signal odata:std_logic_vector(3 downto 0);
signal i : integer:=0;
begin
process(indata,wr,clk,en,wp,clr,i)
begin
if( clk'event and clk='1')then
if (clr='1')then
clean:for i in 0 to 11 loop
ran(wp)<=(others=>'0');
end loop clean;
else
if (en='1' and wr='1' )then
ran(wp)<=ran(wp)+ indata;
else
ran(wp)<=ran(wp);
end if ;
end if;
end if;
end process;
process(clk,wp,clr,wr)
begin
if(clk'event and clk='1')then
if(clr='1')then
wp <=0;
elsif(wp=11)then
wp <=0;
elsif(wr='1')then
wp<=wp+1;
else
null;
end if;
end if;
end process;
process (getin,clk,rd,rp)
begin
if (clk'event and clk='1')then
if (getin='1' and rd='1')then
odata<=ran(rp);
else
null;
end if;
end if;
if(rp=11 or clr='1') then
over<='1';
else
-- rp<=rp+1;
over<='0';
end if;
end process;
process(clk,rp,clr,rd)
begin
if(clk'event and clk='1')then
if(clr='1')then
rp <=0;
elsif(rp=11)then
rp <=0;
elsif(rd='1')then
rp<=rp+1;
else
null;
end if;
end if;
end process;
outdata<=odata when rd='1' else (others=>'0');
overram<=over;
end behav;
【 在 walichun 的大作中提到: 】
: 本人写了一个VHDL程序 ,要求的功能是数据进入后,可以和原来地址的数据求和后,在存如以前的地址,类似于FIFO,但仿真后,输出端,没有输出,想了半天也不明白,请那位高人指点一下. 程序如下.(还有一个数据读的功能)
: library ieee;
: use ieee.std_logic_1164.all;
: ...................
【 在 walichun 的大作中提到: 】
: 本人写了一个VHDL程序 ,要求的功能是数据进入后,可以和原来地址的数据求和后,在存如以前的地址,类似于FIFO,但仿真后,输出端,没有输出,想了半天也不明白,请那位高人指点一下. 程序如下.(还有一个数据读的功能)
: library ieee;
: use ieee.std_logic_1164.all;
: ...................