返回信息流创新实验项目的内容，用的xilinx的FPGA板子，现在在把EDK导入到ISE中，作为一个子模块来用，出现了下面这个问题，求大神大腿啊~~~
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 0
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = 12
List of locked IOB's:
led<5>
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR =
OUTPUT, DRIVE_STR = 12
List of locked IOB's:
Ethernet_Lite_TX_EN
Ethernet_Lite_PHY_RST_N
Ethernet_Lite_MDC
Ethernet_Lite_TXD<0>
Ethernet_Lite_TXD<1>
Ethernet_Lite_TXD<2>
Ethernet_Lite_TXD<3>
ERROR:Place:864 - Incompatible IOB's are locked to the same bank 1
Conflicting IO Standards are:
IO Standard 1: Name = LVCMOS33, VREF = NR, VCCO = 3.30, TERM = NONE, DIR =
BIDIR, DRIVE_STR = 12
List of locked IOB's:
Ethernet_Lite_MDIO
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
感激不尽感激不尽啊~~~~
这是一条镜像帖。来源：北邮人论坛 / embedded-system / #12488同步于 2012/7/12
Embedded_System机器人发帖
求助：ISE中出现的问题 求大神大腿~~
lpy0
2012/7/12镜像同步0 回复
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