返回信息流--主程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY test IS
PORT( player11: IN std_logic_vector(10 downto 0);
host: IN std_logic;
clk: IN std_logic;
choose: IN std_logic;
light1: OUT std_logic_vector(6 downto 0);
light1ten: OUT std_logic_vector(6 downto 0);
light2: OUT std_logic_vector(6 downto 0);
light2ten: OUT std_logic_vector(6 downto 0);
warn: OUT std_logic
);
END test;
ARCHITECTURE test_arc OF test IS
SIGNAL so:std_logic_vector(3 downto 0);
SIGNAL co:std_logic_vector(3 downto 0);
SIGNAL lock:std_logic:='0';
SIGNAL warnlock:std_logic:='0';
SIGNAL count1s:std_logic_vector(3 downto 0);
SIGNAL count1tens:std_logic_vector(3 downto 0);
COMPONENT se_07
PORT(a: IN std_logic_vector(3 downto 0);
b: OUT std_logic_vector(6 downto 0));
END COMPONENT;
BEGIN
PROCESS(player11,host,clk)
VARIABLE count1:std_logic_vector(3 downto 0):="0000";
VARIABLE count1ten:std_logic_vector(3 downto 0):="0011";
BEGIN
IF(host='0') THEN
IF(lock='0') THEN
CASE player11 IS
WHEN "00000000001" => so<="0001";co<="0000";lock<='1';
WHEN "00000000010" => so<="0010";co<="0000";lock<='1';
WHEN "00000000100" => so<="0011";CO<="0000";lock<='1';
WHEN "00000001000" => so<="0100";CO<="0000";lock<='1';
WHEN "00000010000" => so<="0101";CO<="0000";lock<='1';
WHEN "00000100000" => so<="0110";CO<="0000";lock<='1';
WHEN "00001000000" => so<="0111";CO<="0000";lock<='1';
WHEN "00010000000" => so<="1000";CO<="0000";lock<='1';
WHEN "00100000000" => so<="1001";CO<="0000";lock<='1';
WHEN "01000000000" => so<="0000";CO<="0001";lock<='1';
WHEN "10000000000" => so<="0001";CO<="0001";lock<='1';
WHEN OTHERS => so<="1111";CO<="1111";
END CASE;
END IF;
ELSE
so<="1111";CO<="1111";
lock<='0';
END IF;
IF (clk'event and clk='1') THEN
IF(lock='1') THEN
IF(count1="0000") THEN
IF(count1ten/="0000") THEN
IF(count1ten="0001") THEN
warnlock<='1';
END IF;
count1ten:=count1ten-1;
count1:="1001";
ELSE
count1:=count1-1;
END IF;
END IF;
END IF;
END IF;
warn<=warnlock;
count1s<=count1;
count1tens<=count1ten;
END PROCESS;
U0:se_07 PORT MAP(so,light1);
U1:se_07 PORT MAP(co,light1ten);
U2:se_07 PORT MAP(count1tens,light2ten);
U3:se_07 PORT MAP(count1s,light2);
END test_arc;
library ieee;
use ieee.std_logic_1164.all;
ENTITY se_07 IS
PORT(A: IN std_logic_vector(3 downto 0);
B: OUT std_logic_vector(6 downto 0));
END se_07;
ARCHITECTURE se_07_arc OF se_07 IS
BEGIN
PROCESS(A)
BEGIN
CASE A IS
WHEN "0000" => B<="1111110";
WHEN "0001" => B<="0110000";
WHEN "0010" => B<="1101101";
WHEN "0011" => B<="1111001";
WHEN "0100" => B<="0110011";
WHEN "0101" => B<="1011011";
WHEN "0110" => B<="1011111";
WHEN "0111" => B<="1110000";
WHEN "1000" => B<="1111111";
WHEN "1001" => B<="1111011";
WHEN OTHERS => B<="0000000";
END CASE;
END PROCESS;
END se_07_arc;
这是一条镜像帖。来源：北邮人论坛 / circuit / #19325同步于 2011/12/26
该镜像源已超过 30 天没有更新，可能在源站已被删除。
Circuit机器人发帖
以下是我自己写的一个抢答器的程序，但是不计时，感觉很奇怪，
danielinwind
2011/12/26镜像同步2 回复
订阅后，新回复会通过你的通知中心匿名送达。